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E2U0034-28-82
Semiconductor MSM7586-01/03
Semiconductor p/4 Shift QPSK MODEM/ADPCM CODEC
This version: Aug. 1998 MSM7586-01/03 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7586 is a CMOS IC developed for use with digital cordless telephones. The device provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding between the voice band analog signal and 32 kbps ADPCM data. The MSM7586 performs DTMF tone and several types of tone generation, transmit/receive data, mute and gain control, side-tone pass and its gain control, and VOX function.
FEATURES
(p/4 Shift QPSK Modem Unit) * 384 kbps transmission speed * Built-in root Nyquist digital filter for the baseband band limiter * Built-in D/A converters for the analog outputs of the quadrature signal component I and Q * The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs * Completely digitized p/4 shift QPSK demodulator system (ADPCM CODEC Unit) * ADPCM system: built-in ITU-T Recommendations G.726 (32kbps, 24 kbps, 16 kbps) * Transmit/receive full-duplex capability * PCM interface code format: selectable between m-law and A-law * Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps * Transmit/receive mute function; transmit/receive programmable gain setting * Side tone generator (8-step level adjustment) * Built-in DTMF tone, ringing tone, and various ringing tone generators * Built-in VOX function (Common Unit) * Operate with a single 3 V power supply (VDD: 2.7 V to 3.6 V) * Low power consumption When entire system is operating: 20 mA Typ. When powered down: 0.02 mA Typ. * Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7586-01TS-K) (Product name: MSM7586-03TS-K)
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Semiconductor
MSM7586-01/03
BLOCK DIAGRAM
VDDM VDAM RXSC SL1 SL2 DGM AGM
PDN0 PDN1 PDN2 IFIN
AFC RXD
Phase detector
Delay detector
AFC
Decision
RXC
MCK IFCK
SL1 DEC SL2 DPLL
X2
To each block
RPR X1 EXCKM DENM DINM DOUTM R7, R6 R5, R4 I+ I- Q+ Q- 4
CRM1-B7 to B4
+1
MODEM MCU interface
RCW
To each block
SLS BSTO
LPF
-1 +1
D/A
DC Adjust
LPF
ATT
CRM1-B3 to B0
Root Nyquist LPF
D/A
S/P MAPPING
TXD TXW
-1
DC Adjust
ATT
3.84M To D/A CRM0-B6
PLL
TXCI
SGM SGCR Receiver
R
VREF

1/10
384k
TXCO
SGCT IO1 IO2 AIN1- AIN1+ GSX1 AIN2-
SW1
CRC5-B7 CRC5-B6
Transmitter
T
VDAC VOICE DETECT ADPCM CODER P / S S / P P / S S / P P / S S / P VOXO XSYNC IS PCMSI PCMSO BCLK PCMRI PCMRO IR RSYNC EXCKC DENC DINC DOUTC
SW2
- +
- +
T
RC Filter
A/D Convertor
CRC4-B6
CRC2-B6 to B4
BPF
GSX2 AOUT+
-1
ATT
COMPA NDER
DTMF /Tone Generator ATT
R
AOUT- PWI VFRO SAO AIN3 GSX3 AIN4 GSX4
- +
Sign bit
CRC3-B3 to B0 CRC2-B2 to B0
CRC3-B7 to B5
CRC4-B5
RC Filter
D/A Convertor
LPF
+
+ ATT
EXPAN DER To each block
ADPCM DECODER
- +
R
Noise generator
CRC5-B5 CRC5-B4
Power detect To each block
CODEC MCU interface
- +
T
SW3
SW4 SW5
VDDC VDAC DGC AGC PDN3
VOXI
IO3
IO4 IO5
IO6
IO7
TOUT1
TOUT2
TOUT3
RESET
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Semiconductor
MSM7586-01/03
PIN CONFIGURATION (TOP VIEW)
DOUTM 77 EXCKM
100 VDDM
RXSC
DENM
PDN0
PDN1
PDN2
RCW
MCK
IFCK
RPR
RXD
RXC
SLS
IFIN
AFC
NC
NC
NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
NC
X1
X2
85
84
83
82
81
80
79
78
VDAM Q- Q+ I- I+ NC SGM AGM AGC SGCR SGCT AIN1+ AIN1- GSX1 IO5 IO6 IO7 AIN2 GSX2 IO1 IO2 VFRO PWI AOUT- AOUT+
76
DINM
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC TXW TXD TXCO TXCI NC BSTO DGM DGC R7 R6 R5 R4 NC BCLK XSYNC RSYNC NC PCMSO PCMSI IS NC IR PCMRO PCMRI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 VOXI
DOUTC
TOUT1
TOUT2
TOUT3
VDDC
VDAC
PDN3
RESET
GSX4
DINC
AIN3
AIN4
EXCKC
NC : No connect pin 100-Pin Plastic TQFP
VOXO
GSX3
IO3
IO4
DENC
SAO
NC
NC
NC
NC
NC
50
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Semiconductor
MSM7586-01/03
PIN AND FUNCTIONAL DESCRIPTIONS
(Modem Unit) TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CRM0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because this device use APLL to generate an internal clock pulse. When CRM0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied to TXCL, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the TXCL input by 10. The transmit data, synchronous to the 384 kHz clock pulse, should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CRM0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CRM0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) TXW Transmit data window signal input. The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation data is output. (Refer to Fig. 1)
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Semiconductor
(1) CRM0 - B6 = "0"
TXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
(2) CRM0 - B6 = "1"
TXD TXCI (3.84 MHz) TXW TXCO (3.84 kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
Figure 1 Transmit Timing Diagram
, ,
MSM7586-01/03
Dn-1 Dn Ramp rise-up 2 symbols Delay of 6.25 symbols Ramp Fall-down 2 symbols Dn-1 Dn Ramp rise-up 2 symbols Delay of 6.25 symbols Ramp Fall-down 2 symbols
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Semiconductor BSTO BSTO is the modulator side burst window output. The burst position of the I and Q baseband modulator output is output. I+, I-
MSM7586-01/03
Quadrature modulation signal I Component differential analog output. Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control register CRM1 - B7 to B4, and the offset voltage at the I- pin can be adjusted using CRM3 - B7 to B3. Q+, Q- Quadrature modulation signal Q component differential analog outputs. Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control register CRM1 - B3 to B0, and the offset voltage at the Q- pin can be adjusted by using CRM4 - B7 to B3. SGM Internal reference voltage output. The output voltage value is approximately 2.0 V. Insert a bypass capacitor between this pin and the AGM pin. During power down, this output is at 0 V. The external SG voltage if necessary should be used via a buffer.
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Semiconductor PDN0, PDN1, PDN2
MSM7586-01/03
Various power down control. PDN0 controls the standby mode/communication mode; PDN1 controls the modulator unit; and PDN2 controls the demodulator unit. Refer to Table 1 for details. The control register reset input width should be 200ns or more. Table 1: Description of Modem Power Down Control
PDN0 PDN2 PDN1 Standby Mode 0 0 0 Communication Mode 1 0/1 0 1 0 1 0 0 0 Operation State Entire system is powered down. The control register is reset. Entire system is powered down. The control register is not reset. Modulator unit is powered off. (VREF and PLL also powered off.) Demodulator unit is powered on. Modulator unit is powered off. (VREF and PLL are powered on.) I and Q outputs are in a high impedance state. Only the demodulator clock regenerator unit is powered on. 1 1 0 1 1 0 Modulator unit is powered on. Only the demodulator clock regenerator unit is powered on. Modulator unit is powered off. (VREF and PLL are powered off.) I and Q outputs are in a high impedance state. Demodulator unit is powered on. 1 1 1 Modulator unit is powered on. Demodulator unit is powered on. Mode G Mode F Mode E Mode D Mode Name Mode A Mode B Mode C
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Semiconductor VDDM, VDAM
MSM7586-01/03
+3 V power supply for the modem unit. Supplied to the digital circuits through the VDDM pin and to the analog circuits through the VDAM pin. VDDM and VDAM, and VDDC and VDAC should be connected as close as possible on the PC board. DGM, AGM Ground pins for the modem unit. DGM is the ground pin of the digital system, and AGM is the ground pin of the analog system. Since DGM and AGM are isolated inside the IC, connect them as close as possible on the circuit board. MCK Master clock input. The clock frequency is 19.2 MHz. IFIN Modulated signal input for the demodulator block. Select the IF frequency can be selected from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CRM0 - B4 and B3. IFCK Clock frequency 19.0222 MHz input for demodulator block IF frequencies of 10.7 MHz. If the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When supplying a 19.0222 MHz clock to IFCK, use these pins. (Refer to Fig. 2.)
When IFIN = 10.7 MHz When IFIN = 1.2 MHz or 10.8 MHz
MSM7586
MSM7586
X1
X2
IFCK
X1
X2
IFCK
19.0222 MHz
Figure 2 How to Use IFCK, X1, and X2
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Semiconductor RXD, RXC, RXSC
MSM7586-01/03
Receive data and receive clock outputs. When the modem unit is powered on, RXD, RXC and RXSC are selected based on SLS as shown in Figure 3. These outputs are used by the clock regenerator circuit.
RXD RXC RXSC SLS
1 Symbol The regenerated data and clock are selected asynchronously by the SLS signal.
Figure 3 Timing Diagram of RXD, RXC, and RXSC SLS Receive side operation slot selection signal. This device has two clock regenerator circuits and two AFC data memory registers. If SLS is "0", slot 1 is selected, if SLS is "1", slot 2 is selected. RPR High-speed phase clock control signal input for the clock recovery circuit. If this pin is at "0", the circuit is always in the low-speed phase clock mode. If this pin is at "1", the clock recovery circuit enters the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically.
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Semiconductor AFC
MSM7586-01/03
AFC operation range specification signal input. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC operation starts after a fixed number of clock cycles and the AFC information is reset. If RPR is set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC is "0", frequency error is not calculated, but the frequency is corrected using an error that is held. RCW Clock recovery circuit operation ON/OFF control signal input. If RCW this pin is "0", DPLL does not make any phase corrections.
(CASE1) AFC RPR
AFC information is reset. Average number of times AFC is low. Average number of times AFC is high. AFC information is maintained.
(CASE2) AFC RPR
"0" The clock recovery circuit starts with the previous AFC information. Average number of times AFC is high. AFC information is maintained.
Figure 4 AFC Control Timing Diagram
DENM , EXCKM, DINM, DOUTM
Serial control ports for the microprocessor interface. The device contains a 6-byte control register (CRM0 - 5). An external CPU uses these pins to read data from and write data to the control register. DENM is the "Enable" signal input pin. EXCKM is a data shift clock pulse input pin. DINM is an address and data input pin. DOUTM is a data output pin. Figure 5 shows input/output timing diagram.
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Semiconductor
DENM
EXCKM DINM
DOUTM
DENM
EXCKM DINM
DOUTM
The register map is shown below.
Register Name
CRM0 CRM1 CRM2
, ,
MSM7586-01/03
W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 High Impedance (a) Write Data Timing Diagram R A2 A1 A0 High Impedance B7 B6 B5 B4 B3 B2 B1 B0 (b) Read Data Timing Diagram
Figure 5 Modem Unit MCU Interface I/O Timing
Table 2: Modem Unit Control Register (CRM0 to 5) Map
Data Description B4 B3
Address A1 0
A2 0
A0 0
B7 --
B6
B5
B2 --
B1
B0
R/W R/W
TXC SEL Ich
MOD OFF Ich
IFSEL1 Ich
IFSEL0 Qch
TEST1 Qch
TEST0 Qch
0
0
1
Ich
Qch
GAIN3 R7
GAIN2 R6
GAIN1 R5
GAIN0 R4
GAIN3 --
GAIN2 --
GAIN1 --
GAIN0 --
R/W
0
1
0
R/W
CRM3 CRM4 CRM5
0 1 1
1 0 0
1 0 1
Ich
Ich
Ich
Ich
Ich
Offset4 Qch Offset4 ICT5
Offset3 Qch Offset3 ICT4
Offset2 Qch Offset2 ICT3
Offset1 Qch Offset1 ICT2
Offset0 Qch Offset0 LOCAL INV1
--
--
--
R/W R/W R/W
-- LOCAL INV0
-- ICT1
-- ICT0
R/W: Read/Write enable R: Read-only register R7, R6, R5, R4 These are the control register data output pins. These output the data CRM2 - B7, B6, B5, and B4, respectively.
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Semiconductor (CODEC Unit) AIN1+, AIN1-, AIN2, GSX1, GSX2
MSM7586-01/03
The transmit analog input and the output for transmit gain adjustment. The pin AIN1-(AIN2) connects to the inverting input of the internal transmit amplifier, and the pin AIN1+ connects to the non-inverting input of the internal transmit amplifier. The pin GSX1 (GSX2) connects to output of the internal transmit amplifier. See Fig. 6 for gain adjustment. VFRO, AOUT+, AOUT-, PWI Used for the receive analog output and the output for receive gain adjustment. VFRO is an output of the receive filter. AOUT+ and AOUT- are differential analog signal outputs which can directly drive ZL = 350 W+120 nF or the 1.2 kW load. See Fig. 6 for gain adjustment. However, these outputs are in high impedance state during power down. SAO, AIN3, AIN4, GSX3, GSX4 Input pins for the internal operational amp. Refer to Fig. 6 for connection information. However, these output pins are in the high impedance state during power down.
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Semiconductor
MSM7586-01/03
AIN1- Vi C1 R1 Differential analog input signal C1 R1 R2 AIN1+ R2 GSX1 SGCT + - C2 R3 R4 GSX2 AOUT+ AIN2
- +
Reference voltage generator
- + to ENCODER
-1
Z L = 120 nF + 350 W
Analog output signal Vo AOUT-
- +
Transmit gain : (V GSX2 /Vi) = (R2/R1) (R4/R3) Receive gain : (V O /V VFRO ) = 2 (R6/R5)
R6
R5 VFRO +1
from DECODER
SAO R7 Sounder output signal R8 AIN3 GSX3
+1
- +
Sounder output gain : (V GSX3 ) = V SAO (R8/R7)
Figure 6 CODEC Unit Analog Interface
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Semiconductor IO1 to IO7
MSM7586-01/03
I/O pins of the internal analog switch. Refer to the control register description table (CRC5) and the block diagram for connection information and control methods. TOUT1 to TOUT3 Sign bit output pins of the tone generator. Output control of each pin is performed by the control register. Refer to the control register description table (CRC5) and the block diagram for connection information and control methods. SGCT, SGCR Output pins of the CODEC unit analog signal ground voltage. SGCT outputs the analog signal ground voltage of the transmit system, and SGCR outputs the same for the receive system. The output voltage value is approximately 1.4 V. Connect 10 mF and 0.1 mF bypass capacitors (ceramic type) between these pins and the AGC pin. During power down, the output changes to 0 V. The external SG voltage if necessary should be used via a buffer. VDDC, VDAC CODEC unit +3 V power supply. VDDC is supplied to the digital system power supply, and VDAC is supplied to the analog system power supply. VDDC and VDAC, and VDDM and VDAM must be connected as possible on the PC board. DGC, AGC CODEC unit ground. DGC is the digital system ground pin, and AGC is the analog system ground pin. Since DGC and AGC are unconnected in the device, place them as close together as possible on the circuit board. PDN3 CODEC unit power-down control input. The CODEC unit changes to the power - down state when set to a digital "0." Since the powerdown control is handled by an OR with control register CRC0 - B5, set CRC0 - B5 to digital "0" when using this pin. RESET Reset control input pin of the CODEC unit control register. When set to digital "0," each bit of the control register is reset. During normal operation, set this pin to digital "1." A more than 200ns reset signal should be input.
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Semiconductor PCMSO
MSM7586-01/03
Transmit PCM data output. This PCM output signal is output from MSB synchronous with the rising edge of BCLK and XSYNC. PCMSI Transmit PCM data input. This signal is converted to the ADPCM data. The PCM signal is shifted on the falling edge of BCLK. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. The PCM signal is the output signal after ADPCM decoder processing. This signal is serially output from the MSB synchronous with the rising edge of BCLK and RSYNC. PCMRI Receive PCM data input. The PCM input signal is shifted on the falling edge of BCLK and input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. This signal is the output signal after ADPCM encoding, and is serially output from MSB synchronous with the rising edge of BCLK and XSYNC. This pin is an open drain output which remains in a high impedence state during power-down, and requires a pull-up resistor. IR Receive ADPCM signal input. Input data is shifted serially from MSB on the falling edge of BCLK synchronous with RSYNC. BCLK Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data(IS, IR) . The frequency ranges from 64 kHz to 2048 kHz. XSYNC Transmit PCM and ADPCM data 8 kHz synchronous signal input. This signal should be synchronous with BCLK. XSYNC is used for indicating MSB of the transmit serial PCM and ADPCM data stream. RSYNC Receive PCM and ADPCM data 8 kHz synchronous signal input. This signal should be synchronous with BCLK signal. RSYNC is used for indicating MSB of the receive serial PCM and ADPCM data stream.
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Semiconductor VOXO
MSM7586-01/03
Transmit VOX function signal output. VOX function is used to recognize the presence or absence of the transmit voice signal by detecting the signal energy. "H" and "L" levels on this pin correspond to the presence and the absence, respectively. This result also appears at the register data CRC7 - B7. The signal energy detect threshold is set by the control register data CRC6 - B6, B5. VOXI Signal input for receive VOX function. The "H" level on VOXI indicates the presence of voice signal, the decoder block processes normal receive signal, and the voice signal appears at analog output pins . The "L" level indicates the absence of voice signal, the background noise generated in this device is transferred to the analog output pins. The background noise amplitude is set by the control register CRC6. Because this signal is ORed with the register data CRC6 - B3, the control register data CRC6 - B3 should be set to digital "0".
Input voice signal GSX2 pin
VOXO pin
Voice
Silience
Voice
Voice detection time Tvxon
Silence detection time (Hangover time) Tvxoff
(a) Transmission Side VOX Function Timing Diagram
VOXI pin
Voice
Silience
Voice
Regenerated voice VFRO pin
Regenerated voice signal generation time
Internal background noise generation time
(b) Receive Side VOX Function Timing Diagram
Note: The VOXO and VOXI pin function are enabled when CRC6 - B7 is set to "1". Figure 7 VOX Function
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Semiconductor
MSM7586-01/03
DENC, EXCKC, DINC, DOUTC
Serial control ports for MCU interface. Reading and writing data are performed by an external MCU through these pins. The 8-byte control registers (CRC0 - 7) are provided for the CODEC unit in this device. DENC is the "Enable" control signal input, EXCKC is the data shift clock input, DINC is the address and data input, and DOUTC is the data output. Figure 8 shows input/output timing diagram.
DENC
EXCKC DINC
DOUTC
DENC
EXCKC DINC
DOUTC
The register map is shown below.
Register Name
CRC0 CRC1
CRC2
CRC3 CRC4 CRC5 CRC6 CRC7
, ,
W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 High Impedance (a) Write Data Timing Diagram R A2 A1 A0 High Impedance B7 B6 B5 B4 B3 B2 B1 B0 (b) Read Data Timing Diagram
Figure 8 CODEC Unit MCU Interface I/O Timing
Table 3: CODEC Unit Control Register (CRC0 to 7) Map
Data Description B4 -- B3 -- B7 B6 -- B5 B2 --
Address A1 0
A2 0
A0 0
B1 --
B0
R/W R/W
A/m
PDN ALL TX TX
PDN RX
SEL
SAO/AOUT PAD RX
0
0
1
MODE1 TX
MODE0 TX
RX TX
TX
RX
RESET GAIN1 GAIN0 SAO/ VFRO SW3 CONT ON LVL0 LVL0
RESET GAIN0 TONE
MUTE RX
MUTE RX
--
R/W
0
1
0
RX
ON/OFF
GAIN2 GAIN1 TONE SEND SW2 CONT ON LVL1 LVL1
ON/OFF TONE GAIN3
GAIN2 TONE
GAIN1 TONE
GAIN0 TONE
R/W
0
1
1
Side Tone Side Tone Side Tone GAIN2 DTMF/ OTHERS SEL SW1 CONT VOX ON/OFF VOX OUT
ON/OFF TONE4 SW4/5 CONT OFF TIME --
GAIN2
GAIN1
GAIN0
R/W
1 1 1 1
0 0 1 1
0 1 0 1
TONE3 -- VOX IN --
TONE2 TOUT3 CONT LEVEL SEL --
TONE1 TOUT2 CONT LVL1 --
TONE0 R/W TOUT1 CONT LVL0 -- R/W R/W R
RX NOISE RX NOISE RX NOISE
TX NOISE TX NOISE
R/W: Read/Write enable R: Read-only register 17/42
Semiconductor
MSM7586-01/03
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition -- -- -- -- Rating -0.3 to +5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Digital Output Load Bypass Capacitor for SG Master Clock Frequency Master Clock Duty Ratio Modulator Side Input Frequency
Modem Unit
Symbol VDD Ta VIH VIL tIr tIf RDL CDL CSG FMCK FTXC1 FTXC2 FIFCK1 FIFCK2 DCIF
Conditon Voltage must be fixed -- Input pins fully digital Input pins fully digital Input pins fully digital Input pins fully digital IS (Pull-up resistance) Input pins fully digital Between SGM and AGM, and between SGCT/R and AGC MCK TXCI (When CRM0 - B6 = "0") TXCI (When CRM0 - B6 = "1") IFCK (When IFIN = 10.7 MHz) IFCK (When IFIN = 10.75 MHz) IFIN Fig.9
Min. 2.7 -25 0.45 VDD 0 -- -- 500 -- 10 + 0.1 -0.01% 40 -- -- -- -- 40 45 200 200 64 -- 40 100 100 Fig.12 1 BCLK 100 100
Typ. -- +25 -- -- -- -- -- -- -- 19.2 50 384 3.84 19.0222 19.1111 50 50 -- -- -- 8.0 50 -- -- -- -- --
Max. 3.6 +70 VDD 0.16 VDD 50 50 -- 100 -- +0.01% 60 -- -- -- -- 60 55 -- -- 2048 -- 60 -- -- 100 -- --
Unit V C V V ns ns W pF mF MHz % kHz MHz MHz MHz % % ns ns kHz kHz % ns ns ms ns ns
DMCK MCK
Demodulator Side Input Frequency Clock Duty Ratio IF Input Duty Ratio Transmit Sync Pulse Setting Time Bit Clock Frequency Synchronous Signal Frequency Clock Duty Ratio
DCKM IFCK, TXCI, EXCKM
tXSM, tSXM TXCITXW tSDM, tDHM TXCITXD
FBCK DCKC
BCLK BCLK, EXCKC
FSYNC XSYNC, RSYNC
CODEC Unit
Transmit Sync Pulse Setting Time tXSC, tSXC BCLKXSYNC
Receive Sync Pulse Setting Time tRSC, tSRC BCLKRSYNC tWSC XSYNC, RSYNC Synchronous Signal Width PCM, ADPCM Set-up Time PCM, ADPCM Hold Time tDSC tDHC -- --
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Semiconductor
MSM7586-01/03
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Symbol IDD1 Power Supply Current (Modem Unit) * When CODEC Unit is in a Power Down State Power Supply Current (CODEC Unit) * When Modem Unit is in a Power Down State Input Leakage Current Output High Voltage Output Low Voltage Output Leakage Current Input Capacitance IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 IIH IIL VOH VOL IO CIN Condition Mode A, Mode B (When VDD = 3.0 V) Mode C (When VDD = 3.0 V) Mode D (When VDD = 3.0 V) Mode E (When VDD = 3.0 V) Mode F (When VDD = 3.0 V) Mode G (When VDD = 3.0 V) When operating * (When no signal, and VDD = 3.0 V) When powered down (When VDD = 3.0 V) VI = VDD VI = 0 V IOH = 0.4 mA IOH = 1 mA IOL = -1.2 mA (IS pin is 500 W pull-up) IS pin -- Min. -- -- -- -- -- -- -- -- -- -- -- 0.5 VDD 0.8 VDD 0 -- -- Typ. 0.02 5.5 5.5 11.5 9.5 14.0 8.0 12.0 0.02 -- -- -- -- 0.2 -- 5 Max. 0.1 11.0 11.0 23.0 19.0 28.0 16.0 19.0 0.1 2.0 0.5 VDD VDD 0.4 10 -- Unit mA mA mA mA mA mA mA mA mA mA mA V V V mA pF
*
IDD7 applies when CRC0 - B0 = "0" and CRC4 - B5 = "0"; IDD8 applies when operating at other times.
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Semiconductor Analog Interface Characteristics (Modem Unit)
MSM7586-01/03
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Output Resistance Load Output Capacitance Load Output DC Voltage Level Output AC Voltage Level Offset Voltage Difference Modulator D/A Conversion Sampling Frequency Modulator D/A Conversion Offset Frequency Output DC Voltage Adjustment Level Range Output AC Voltage Adjustment Level Range Out-of-band Spectrum Modulation Accuracy Demodulator Side IF Input Level IFIN Input Impedance SGM Output Voltage SGM Output Impedance Symbol RLIQ CLIQ Condition I+, I-, Q+, Q- I+, I-, Q+, Q- I+, I-, Q+, Q- (For TXD = 0 continuous input) Difference among I+, I-, Q+ and Q- -- -- -- -- Min. 10 -- 1.55 340 -20 -- -- -- -- 60 65 -- 0.4 -- -- -- 1.5 0.7 -- -- Typ. -- -- 1.6 360 -- 1.92 380 45 4 -- -- 1.0 -- 20 2.0 1.5 -- -- 2.0 10 Max. -- 20 1.65 380 +20 -- -- -- -- -- -- 3.0 VDD -- -- -- VDD VDD -- -- Unit kW pF V mVPP mV MHz kHz mV % dB dB % rms VPP kW V kW VPP VPP MW pF
VDCM I+, I-, Q+, Q- (TXW = 0) VACM VOFF FSDA FCDA DCVL ACVL
P600 600 kHz detuning (continuous) P900 900 kHz detuning (continuous) EVM IFV RIF VSGM RSGM IX11 X1 input level (When CRM5 - B1 = "0") X1 input level (When CRM5 - B1 = "1") -- -- -- IFIN input level DC impedance -- --
Master Clock External Input Level IX12 X1 Input Impedande X1 Input Capacitance RX1 CX1
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Semiconductor Digital Interface Characteristics (Modem Unit)
MSM7586-01/03
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Transmit Digital I/O Setting Time Receive Digital I/O Setting Time Symbol Condition Reference Fig. 9 Fig. 10 Min. 0 0 0 50 50 50 50 100 C load = 50 pF Fig. 11 50 50 0 50 50 0 200 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 200 400 200 -- -- -- -- -- -- -- 100 -- -- 50 -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz tXDM1,2 C load = 50 pF tXDM3,4 tRDM1,2 C load = 50 pF tM1 tM2 tM3 tM4 Serial Port Digital I/O Setting Time tM5 tM6 tM7 tM8 tM9 tM10 tM11 tM12 EXCK Clock Frequency Feckm EXCKM
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Semiconductor Analog Interface Characteristics (CODEC Unit)
MSM7586-01/03
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Input Resistance Symbol RINC RLC1 Output Resistance Load RLC2 RLC3 CLC1 Output Capacitance Load CLC2 CLC3 VOC1 Output Voltage Level (*1) VOC2 VOC3 Offset Voltage SGCT, SGCR Output Voltage SGCT Output Impedance SGCR Output Impedance SGCT Rise Time SGCR Rise Time Analog Switch OFF Resistance Analog Switch ON Resistance Condition AIN+, AIN-, AIN2, PWI, AIN3, AIN4 GSX1, GSX2, VFRO, SAO AOUT+, AOUT-, GSX4 GSX3 GSX1, GSX2, VFRO, SAO AOUT+, AOUT-, GSX4 GSX3 GSX1, GSX2, VFRO, SAO(RL = 20 kW) AOUT+, AOUT-, GSX4 (RL = 1.2 kW) GSX3(RL = 150 W) GSX1, GSX2, AOUT+, AOUT-, GSX3, GSX4 SGCT, SGCR Min. 10 20 1.2 150 -- -- -- -- -- -- -100 -20 -- -- -- -- -- 50 100 Typ. -- -- -- -- -- -- -- -- -- -- -- -- 1.4 40 4 600 15 -- -- Max. -- -- -- -- 100 100 100 1.3 1.3 1.3 +100 +20 -- 80 8 -- -- -- 400 Unit MW kW kW W pF pF pF VPP VPP VPP mV mV V kW kW ms ms MW W
VOFC1 VFRO, SAO VOFC2 VSGC
RSGCT SGCT RSGCR SGCR TSGCT TSGCR For the Recommended Circuit (Rise time to 90% of max. level) For the Recommended Circuit (Rise time to 90% of max. level)
RSWof SW1 to SW5 RSWon SW1 to SW5
Note :
*1
-7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0 = 1.30 VPP (A-law) -7.7 dBm (600 W) = 0 dBm0, +3.17 dBm0 = 1.30 VPP (m-law)
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Semiconductor Digital Interface Characteristics (CODEC Unit)
MSM7586-01/03
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Digital Output Delay Time PCM, ADPCM Interface Symbol tSDXC, tSDRC tXDC1, tRDC1 tXDC2, tRDC2 tXDC3, tRDC3 tC1 tC2 tC3 tC4 tC5 Serial Port Digital I/O Timing Characteristics tC6 tC7 tC8 tC9 tC10 tC11 tC12 EXCK Clock Frequency Feckc EXCKC -- C load = 50 pF Fig. 13 Condition Reference Min. 0 0 0 0 50 50 50 50 100 50 50 0 50 50 0 200 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 200 (100) 200 (100) 200 (100) 200 (100) -- -- -- -- -- -- -- 100 -- -- 50 -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 1 LSTTL + 100 pF pull-up : 500 W Fig. 12 Items in parenthesis ( ) mean C load = 10 pF, and the pull-up 2 kW
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Semiconductor AC Characteristics (CODEC Unit)
Parameter Symbol LOSS T1 LOSS T2 Transmit Frequency Response LOSS T3 LOSS T4 LOSS T5 LOSS T6 LOSS R1 Receive Frequency Response LOSS R2 LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Distortion Ratio (*2) SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Distortion Ratio (*2) SD R2 SD R3 SD R4 SD R5 GT T1 Transmit Gain Tracking GT T2 GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking GT R2 GT R3 GT R4 GT R5 1020 1020 1020 1020 Condition Frequency (Hz) 0 to 60 300 to 3 k 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -0.2 -0.5 -1.2 -0.2 -0.5 -1.2 -0.2 0 -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.2 0 Level dBm0
MSM7586-01/03
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. 25 -0.15 -0.15 0 13 -0.15 Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- +0.2 +0.5 +1.2 +0.2 +0.5 +1.2 +0.2 +0.80 0.80 -- -- -- -- -- -- -- -- -- -- -- +0.2 +0.80 0.80 -- +0.20 Max. -- +0.20 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Note:
*2
P-message filter used
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Semiconductor AC Characteristics (CODEC Unit)
Parameter Idle Channel Noise (*2) Absolute Level (*4) Power Supply Noise Rejection Ratio NIDLR AVT AVR PSRRR -- 1020 (*3) 0 Noise level: 50 mVpp -- GSX2 VFRO -- -- 0.285 0.285 30 30 -- Symbol NIDLT Condition Frequency (Hz) -- Level dBm0 AIN = SG Other --
MSM7586-01/03
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -- Typ. -- Max. -68 (-75.7) -72 (-79.7) 0.359 0.359 -- -- Vrms Vrms dB dB dBm0p (dBmp) Unit
0.320 0.320 -- --
PSRRT Noise frequency: 0 kHz to 50 kHz
*2 P-message filter used *3 PCMRI input: "11010101" (A-law), "11111111" (m-law) *4 0.320 Vrms = 0 dBm0 = -7.7 dBm (600 W) ADPCM unit characteristics are fully compliant with ITU-T Recommendation G.726. AC Characteristics (DTMF and Other Tones)
Parameter Frequency Deviation Tone Reference Output Level (*5) Symbol DFT1 DFT2 VTL VTH VRL VRH DTMF tones Other various tones Transmit side tone DTMF (low group) (Gain setting 0dB) DTMF (high group), other Receive side tone DTMF (low group) (Tone generator gain setting -6dB) DTMF (high group), other VTH/VTL, VRH/VRL Condition (VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -7 -7 -18 -16 -10 -8 1 Typ. -- -- -16 -14 -8 -6 2 Max. +7 +7 -14 -12 -6 -4 3 Unit Hz Hz dBm0 dBm0 dBm0 dBm0 dB
Notes:
DTMF Tone Level Relative Value RDTMF
Note:
*5 Not including programmable gain set values
AC Characteristics (Gain Settings)
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Transmit/Receive Gain Setting Accuracy Symbol DG Condition For all gain set values Min. -1 Typ. 0 Max. +1 Unit dB
AC Characteristics (VOX Function)
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Transmit VOX Detection Time (Voice and Silence Test Time) Transmit VOX Detection Level Accuracy (Voice Detection Level) DVX Symbol TVXON TVXOF Condition SilenceAEvoice VOXO pin: See Fig. 7 VoiceAEsilence Voice/silence differential: 10 dB Min. -- Typ. 10*6 Max. -- Unit ms ms
140/300 160/320 180/340
For detection level set values by CRM6 - B6, B5
-2.5
0
+2.5
dB
Note:
*6 When single tone is input at 1000Hz 25/42
Semiconductor
TIMING DIAGRAM
(Modem Unit) Transmit Data Input Timing
TXCI [TXCO*] (384 kHz) TXW TXD 1
Transmit Clock (TXCO) Timing (When CRM0 - B6 = 1)
TXCI (3.84 MHz) TXCO (384 kHz) 1 2 3 4 5
Transmit Burst Position (BSTO) Output Timing (When CRM0 - B6 = 0)
TXCI (384 kHz) TXW 1 2 9 10 N N+1
, ,
MSM7586-01/03
2 3 N-2 N-1 N N+1
tXSM
tSXM
tXSM
tSXM
tDSM tDHM
1
2
3
N-2
N-1
N
TXCO in brackets [ ] is when CRM0 - B6 = 1
6
7
8
9
10
tXDM1
tXDM2
tXDM1
N+16
N+17
N+18
tXDM3
BSTO
tXDM4
Figure 9 Modem Unit Transmit Side (Modulator Side) Digital I/O Timing Receive Side Data I/O Timing
SLS RXC
tRDM1
RXD
tRDM2
Figure 10 Modem Unit Receive Side (Demodulator Side) Digital I/O Timing Serial Port Timing for Microcontroller Interface
DENM tM2 EXCKM tM1 DINM 1 tM3 tM4 W/R A2 2 3 tM6 4 tM7 tM5 5 6 11 12 tM9 tM12 tM10
A1
A0
B7 tM8
B1
B0 tM11
DOUTM
B7
B1
B0
Figure 11 Modem Unit Serial Control Port Interface
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Semiconductor (CODEC Unit) Transmit Side PCM, ADPCM Timing
BCLK XSYNC PCMSO BCLK XSYNC IS tSDXC 0 tXSC 0 tXSC 1 tSXC tXDC1 MSB tSDXC 1 tSXC tXDC1 MSB 2 3 4 5 6 7 8 2 tWSC tXDC2 3 4 5 6 7 8
MSM7586-01/03
9
10
tXDC3 LSB
9
10
tXDC2
tXDC3 LSB
Receive Side PCM, ADPCM Timing
BCLK tRSC RSYNC tDSC IR BCLK RSYNC tRDC1 PCMRO MSB tSDXC tRDC2 tRDC3 LSB MSB 0 tRSC 1 tSRC 2 3 4 1 tSRC 2 3 tWSC tDHC LSB 5 6 7 8 9 10 4 5 6 7 8 9 10
tXDC3
Figure 12 CODEC Unit PCM, ADPCM Interface Serial Port Timing for Microcontroller Interface
DENC tC2 EXCKC tC1 DINC tC3 1 tC4 W/R A2 2 3 tC6 4 tC7 tC5 5 6 11 12 tC9 tC12 tC10
A1
A0
B7 tC8
B1
B0 tC11
DOUTC
B7
B1
B0
Figure 13 CODEC Unit Serial Control Port Interface
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Semiconductor Modem Unit Mode State Transition Time
Mode A* Note: Values not indicated are less than 1 ms.
PDN1 = 1
MSM7586-01/03
1 ms
Mode B
5 ms
Mode C
PDN1 = 0 PDN2 = 1
Standby mode (PDN0 = 0) Communication mode (PDN0 = 1)
40 ms
PDN1 = 0 PDN2 = 0
5 ms
Mode E
PDN1 = 1 PDN2 = 0 5 ms
Mode D
PDN1 = 0 PDN2 = 0 40 ms
Mode F
PDN1 = 0 PDN2 = 1
Mode G
PDN1 = 1 PDN2 = 1
* Note that this state clears the register.
Figure 14 Modem Unit Power Down State Transition Time
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Semiconductor Modem Unit Demodulator Control Timing Diagram (Example)
Demodulator unit Modulator input data 1st slot
G R1 G
MSM7586-01/03
PDN2
SLS AFC RXD RXC
"0"
(1) Control ch/ synchronous burst (SS + PR = 64 bits)
RXD
AFC* RPR
RCW*
(2) When synchronization is not yet established
AFC* RPR
RCW*
(3) Communication ch (SS + PR = 8 bits)
RXD AFC RPR RCW
G

R1 240 bits 625 ms 64 bits G G G G G G G G R R R R SS SS PR PR PR UW CR CR G G G G G G G G 56 bits 8 bits G G G G G G R R R R SS SS PR PR PR UW CR CR G G G G G G G G G "0"
Less than 30 bits
*AFC and RCW may be controlled at the same timing.
G: Guard bit R: Ramp bit SS: Start symbol bit PR: Preamble bit UW: Unique word bit CR: CRC bit
Figure 15 Modem Unit Demodulator Timing Diagram Example
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Semiconductor
MSM7586-01/03
FUNCTIONAL DESCRIPTION
Control Register Description Table (Modem Unit) (1) CRM0 (Basic Operation Mode Setting)
B7 CRM0 Initial Value (Note) -- 0 B6 TXC SEL 0 B5 MOD OFF 0 B4 IFSEL1 0 B3 IFSEL0 0 B2 -- 0 B1 TEST1 0 B0 TEST0 0
Note:
The initial value is the value set when a reset is applied by the RESET pin. B7, B2: ..... Not used B6: ............ Transmission timing clock selection 0: TXCI input: 384 kHz TXCO output: APLL 384 kHz output Transmission data TXD is input synchronized to the rise of TXCI. APLL is ON. 1: TXCI input: 3.84 MHz TXCO output: 384 kHz (TXCI divided by 10) Transmission data TXD is input synchronized to the rise of TXCO. APLL is OFF. B5: Modulation OFF/ON control 0: Modulation ON 1: Modulation OFF B4, B3: ..... Receive side input IF frequency selection (0,0), (0,1): 1.2 MHz (1,0): 10.8 MHz (1,1): 10.7 MHz/10.75 MHz B1, B0: ..... Device test control bit Since it is used for LSI testing, it is normally set to "0."
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Semiconductor (2) CRM1 (I and Q Gain Adjustment)
B7 CRM1 Initial Value Ich GAIN3 0 B6 Ich GAIN2 0 B5 Ich GAIN1 0 B4 Ich GAIN0 0 B3 Qch GAIN3 0 B2 Qch GAIN2 0
MSM7586-01/03
B1 Qch GAIN1 0
B0 Qch GAIN0 0
B7 to B4: .... I+ and I- output gain setting: 3 mV steps (refer to Table 4) B3 to B0: .... Q+ and Q- output gain setting: 3 mV steps (refer to Table 4) Table 4: I and Q Gain Setting Table
CRM1 - B7 CRM1 - B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B6 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B5 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B4 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description Amplitude value: 1.042 reference value 1.036 1.030 1.024 1.018 1.012 1.006 1.000 (Reference value) 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952
(3) CRM2 (Output to R7 to R4 pins)
B7 CRM2 Initial Value R7 0 B6 R6 0 B5 R5 0 B4 R4 0 B3 -- 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B4: .... Output to R7 to R4 pin
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MSM7586-01/03
(4) CRM3 (I- Output Offset Voltage Adjustment)
B7 CRM3 Initial Value Ich Offset4 0 B6 Ich Offset3 0 B5 Ich Offset2 0 B4 Ich Offset1 0 B3 Ich Offset0 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B3: .... I- output pin offset voltage adjustment (refer to Table 5) B2 to B0: .... Not used (5) CRM4 (Q- Output Offset Voltage Adjustment)
B7 CRM4 Initial Value Qch Offset4 0 B6 Qch Offset3 0 B5 Qch Offset2 0 B4 Qch Offset1 0 B3 Qch Offset0 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B3: .... Q- output pin offset voltage adjustment (refer to Table 5) B2 to B0: .... Not used Table 5: Ich and Qch Offset Adjustment Values
CRM3 - B7 B6 B5 B4 B3 CRM4 - B7 B6 B5 B4 B3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +45 mV +42 mV +39 mV +36 mV +33 mV +30 mV +27 mV +24 mV +21 mV +18 mV +15 mV +12 mV +9 mV +6 mV +3 mV 0 mV Offset Voltage CRM3 - B7 B6 B5 B4 B3 CRM4 - B7 B6 B5 B4 B3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -3 mV -6 mV -9 mV -12 mV -15 mV -18 mV -21 mV -24 mV -27 mV -30 mV -33 mV -36 mV -39 mV -42 mV -45 mV -48 mV Offset Voltage
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Semiconductor
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(6) CRM5 (IC Test)
B7 CRM5 Initial Value ICT5 0 B6 ICT4 0 B5 ICT3 0 B4 ICT2 0 B3 LOCAL INV1 0 B2 LOCAL INV0 0 B1 ICT1 0 B0 ICT0 0
Note:
B7 to B4: .... LSI test control bit Since B7 to B4 of CRM5 are used for LSI testing, they should normally be set to "0". B3, B2: .......Local inverted mode setting bit (Use if the phase of the demodulator side IF input is inverted due to the system configuration.) (0,0): Normal mode(1,1): Local inverted mode B1: .............. Waveform shaping mode switching bit of the oscillator circuit unit clock (When using a master clock external input, increase the X1 pin input sensitivity.) 0: Normal mode 1: Clock waveform shaping mode B0: .............. Oscillator circuit unit power on control bit 0: Normal mode 1: Oscillator circuit unit is always powered on
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Semiconductor
MSM7586-01/03
(CODEC Unit) (1) CRC0 (Basic Operation Mode Settings)
B7 CRC0 Initial Value A/m SEL 0 B6 -- 0 B5 PDN ALL 0 B4 -- 0 B3 -- 0 B2 -- 0 B1 -- 0 B0 PDN SAO/AOUT 0
B7: ........................... PCM interface companding selection 0: m-law 1: A-law B6, B4, B3, B2, B1: . Not used (These pins are used to test the device. They should be set to "0" during normal operation.) B5: ........................... Power down (entire unit) 0: Power ON 1: Power down ORed with the inverse of the external power down signal. When using this data, set PDN3 to "1." B0: ........................... The sounder output amp (SAO, GSX3) and receiver system output amp (VFRO, AOUT+, AOUT-) power down control 0: The output amp of the side not selected by CRC4 - B5 is powered down. 1: The sounder system output amp and receiver system output amp are both powered ON. (2) CRC1 (ADPCM Unit Operation Mode Settings)
B7 CRC1 Initial Value MODE1 0 B6 MODE0 0 B5 TX RESET 0 B4 RX RESET 0 B3 TX MUTE 0 B2 RX MUTE 0 B1 -- 0 B0 RX PAD 0
B7, B6: .......ADPCM unit compression algorithm selection (0,0): 32 kbps (0,1): 64 kbps (G.711 through) (1,0): 24 kbps (1,1): 16 kbps B5: .............. Transmit side ADPCM reset (according to the G.726 specifications): 1: Reset The ADPCM reset input width should be 125 ms or more. B4: .............. Receive side ADPCM reset (according to the G.726 specifications): 1: Reset The ADPCM reset input width should be 125 ms or more. B3: .............. Transmit side ADPCM data mute: 1: Mute B2: .............. Receive side ADPCM data mute: 1: Mute B1: .............. Not used B0: .............. Receive side PAD 0: No PAD 1: A PAD with a 12 dB loss is inserted in the receive side voice path
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Semiconductor
MSM7586-01/03
(3) CRC2 (PCM CODEC Unit Operation Mode Settings and Transmit/Receive Gain Adjustment)
B7 CRC2 Initial Value TX ON/OFF 0 B6 TX GAIN2 0 B5 TX GAIN1 1 B4 TX GAIN0 1 B3 RX ON/OFF 0 B2 RX GAIN2 0 B1 RX GAIN1 1 B0 RX GAIN0 1
B7: .............. Transmit side PCM signal ON/OFF 0: ON 1: OFF When OFF, transmits a PCM idle pattern. B6, B5, B4: Transmit side signal gain adjustment (refer to Table 6) B3: .............. Receive side PCM signal ON/OFF 0: ON 1: OFF When OFF transmits a PCM idle pattern. B2, B1, B0: .Receive side signal gain adjustment (refer to Table 6) Table 6: Receive/Transmit Gain Settings * MSM7586-01
B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Transmit Side Gain -6 dB -4 dB -2 dB 0 dB +2 dB +4 dB +6 dB +8 dB B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive Side Gain -6 dB -4 dB -2 dB 0 dB +2 dB +4 dB +6 dB +8 dB
* MSM7586-03
B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Transmit Side Gain -6 dB -4 dB -2 dB 0 dB +2 dB +4 dB +6 dB +8 dB B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive Side Gain -12 dB -9 dB -6 dB -3 dB 0 dB +3 dB +6 dB +9 dB
The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled by CRC4 - B6 (discussed later), and the gain setting is set to the levels shown below. DTMF tones (low group): ................................. -16 dBm0 DTMF tones (high group) and other tones: ... -14 dBm0 For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1, 1, 1), then the following tones appear at the PCMSO pin. DTMF tones (low group): ................................. -8 dBm0 DTMF tones (high group) and other tones: ... -6 dBm0 35/42
Semiconductor
MSM7586-01/03
However, the gain of the receive side tone and the gain of the side tones (path from transmit side to receive side) are set by the CRC3 register. (4) CRC3 (Side Tone and Tone Generator Gain Adjustment)
B7 CRC3 Initial Value GAIN2 0 B6 GAIN1 0 B5 GAIN0 0 B4 TONE ON/OFF 0 B3 TONE GAIN3 0 B2 TONE GAIN2 0 B1 TONE GAIN1 0 B0 TONE GAIN0 0
Side Tone Side Tone Side Tone
B7, B6, B5: ........ Side tone gain adjustment (refer to Table 7) B4: ..................... Tone generator ON/OFF 0: OFF 1: ON B3, B2, B1, B0: . Tone generator Receive side gain adjustment (refer to Table 8) Table 7: Side Tone Gain Settings * MSM7586-01
B7 0 0 0 0 1 1 1 1 B6 0 0 1 1 0 0 1 1 B5 0 1 0 1 0 1 0 1 Side Tone Gain OFF -21 dB -19 dB -17 dB -15 dB -13 dB -11 dB - 9 dB
* MSM7586-03
B7 0 0 0 0 1 1 1 1 B6 0 0 1 1 0 0 1 1 B5 0 1 0 1 0 1 0 1 Side Tone Gain OFF -15 dB -13 dB -11 dB - 9 dB - 7 dB - 5 dB - 3 dB
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Semiconductor Table 8: Receive Side Tone Generator Gain Settings * MSM7586-01
B3 0 0 0 0 0 0 0 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain -36 dB -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1
MSM7586-01/03
Tone Generator Gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB - 8 dB - 6 dB
* MSM7586-03
B3 0 0 0 0 0 0 0 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain OFF -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB - 8 dB - 6 dB
The receive side tone generator gain settings shown in Table 8 are set with the following levels as a reference. DTMF tones (low group): ................................. -2 dBm0 DTMF tones (high group) and other tones: ... 0 dBm0 For example, if the tone generator gain set value is set to -6 dB (B3, B2, B1, B0)=(1, 1, 1, 1), then tones at the following levels appear at the SAO or VFRO pin. DTMF tones (low group): ................................. -8 dBm0 DTMF tones (high group) and other tones: ... -6 dBm0
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Semiconductor (5) CRC4 (Tone Generator Operation Mode and Frequency Settings)
B7 CRC4 Initial Value DTMF/OT HERS SEL 0 B6 TONE SEND 0 B5 SAO/ VFRO 0 B4 TONE4 0 B3 TONE3 0 B2 TONE2 0
MSM7586-01/03
B1 TONE1 0
B0 TONE0 0
B7: ........................... Selection of DTMF signal and other tones (S tone, F tone, R tone, etc.) 0: Other tones 1: DTMF tones B6: ........................... Transmission side tone transmit 0: Voice signal transmit 1: Tone transmit B5: ........................... Receive side tone output pin selection 0: VFRO output 1: SAO output B4, B3, B2, B1, B0: . Tone frequency setting (refer to Table 9) Table 9: Tone Generator Frequency Settings (a) When B7 = 1 (DTMF Tones)
B4 * * * * * * * * B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Description 697 Hz + 1209 Hz 697 Hz + 1336 Hz 697 Hz + 1477 Hz 697 Hz + 1633 Hz 770 Hz + 1209 Hz 770 Hz + 1336 Hz 770 Hz + 1477 Hz 770 Hz + 1633 Hz B4 * * * * * * * * B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Description 852 Hz + 1209 Hz 852 Hz + 1336 Hz 852 Hz + 1477 Hz 852 Hz + 1633 Hz 941 Hz + 1209 Hz 941 Hz + 1336 Hz 941 Hz + 1477 Hz 941 Hz + 1633 Hz
(b) When B7 = 0 (Outside of DTMF Tones)
B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description 2730 Hz/2500 Hz 8 Hz Wamble 2000 Hz/2667 Hz 8 Hz Wamble 1000 Hz/1333 Hz 8 Hz Wamble -- -- -- -- -- -- 400 Hz Single tone -- -- -- -- -- 1000 Hz Single tone B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description -- 1300 Hz Single tone 1333 Hz Single tone -- -- 2000 Hz Single tone -- -- -- -- -- -- 2667 Hz Single tone -- 2730 Hz Single tone --
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Semiconductor (6) CRC5 (Control of Switches, etc.)
B7 CRC5 Initial Value SW1 CONT 0 B6 SW2 CONT 0 B5 SW3 CONT 0 B4 SW4/5 CONT 0 B3 -- 0 B2 TOUT3 CONT 0
MSM7586-01/03
B1 TOUT2 CONT 0
B0 TOUT1 CONT 0
B7, B6: .......SW1, SW2 control B5: .............. SW3 control B4: .............. SW4/5 control B2, B1, B0: .TOUT3 to 1 control
0: Open 1: Closed 0: Open 1: Closed 0: SW4 open, SW5 closed 1: SW4 closed, SW5 open 0: TOUT3 to 1 disable 1: TOUT3 to 1 enable
(7) CRC6 (VOX Function Control)
B7 CRC6 Initial Value VOX ON/OFF 0 B6 ON LVL1 0 B5 ON LVL0 0 B4 OFF TIME 0 B3 VOX IN 0 B2 RX NOISE LEVEL SEL 0 B1 RX NOISE LVL1 0 B0 RX NOISE LVL0 0
B7: .............. VOX function ON/OFF 0: OFF 1: ON B6, B5: .......Transmit side voice/silence detector level settings (For the signal of 1kHz) MSM7586-01 (0,0): -30 dBm0 (0,1): -35 dBm0 (1,0): -40 dBm0 (1,1): -45 dBm0 MSM7586-03 (0,0): -20 dBm0 (0,1): -26 dBm0 (1,0): -32 dBm0 (1,1): -38 dBm0 B4: .............. Hangover time (refer to Fig. 7) settings 0: 160 ms 1: 320 ms B3: .............. Receive side VOX input signal 0: Internal background noise transmit 1: Voice receive signal transmit When using this data, set the VOXI pin to "0." B2: .............. Receive side background noise level setting 0: Internal automatic setting 1: External (by B1, B0) setting Internal automatic setting AE Sets to the voice signal level when B3 (VOXI) changes from "1" to "0." B1, B0: .......External setting background noise level (0,0): No noise (0,1): -55 dBm0 (1,0): -45 dBm0 (1,1): -35 dBm0
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Semiconductor (8) CRC7 (Detect Register: Read-only)
B7 CRC7 Initial Value VOX OUT 0 B6 1 0 B5 0 0 B4 -- * B3 -- * B2 -- *
MSM7586-01/03
B1 -- *
B0 -- *
Silent Level Silent Level
Note:
B7: ........................... Transmit side voice/silence detection 0: Silence 1: Voice B6, B5: .................... Transmit side silence level (indicator) MSM7586-01 (0,0):Below -60 dBm0 (0,1): -50 to -60 dBm0 (1,0): -40 to -50 dBm0 (1,1): Above -40 dBm0 MSM7586-03 (0,0):Below -50 dBm0 (0,1): -40 to -50 dBm0 (1,0): -30 to -40 dBm0 (1,1): Above -30 dBm0 These outputs are enabled when the VOX function is turned ON by CRC6 - B7. B4, B3, B2, B1, B0: . Not used
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Semiconductor
MSM7586-01/03
APPLICATION CIRCUIT
MSM7586
100 1 30 29 7 10 11
10 mF 10 mF 10 mF
VDDM VDAM VDDC VDAC SGM SGCR SGCT AGC DGC AGM DGM IFIN Q- Q+ I- I+ AIN1+ AIN1- GSX1 AIN2 GSX2 AOUT+ AOUT-
PDN2 PDN1 PDN0 DENM EXCKM DOUTM DINM BSTO TXCI TXCO TXD TXW RXD RXC RPR AFC RCW SLS RXSC PDN3 RESET DINC DOUTC EXCKC DENC BCLK XSYNC RSYNC PCMSO PCMSI IS IR PCMRO PCMRI
87 88 89 79 78 77 76 69 71 72 73 74 81 82 83 84 85 98 99 41 42 44 45 46 47 61 60 59 57 56 55 53 52 51 49 50 VDDC 500 W
1 mF
1 mF
1 mF
1 mF
-
-
1 mF
+
+
+ -
9 8
67 68 1000 pF 97 2 RF 3 4 5 12 13 14 R3 18 R4 19 25 Speaker R6 24 23
MODEM CONT.
MIC
1 mF
R1 R2
SGCT
R8 Sounder
Ringer
PWI R5 22 VFRO R7 26 SAO 27 AIN3 28 GSX3 32 AIN4 33 GSX4 38 TOUT1 39 TOUT2 40 TOUT3 90 91 95 92 MCK IFCK X1 X2
ADPCM CODEC CONT.
19.2 MHz
VOXI VOXO
R1 Output drive resistance of MIC R2//R3 20 kW R4, R5, R7 20 kW R6//Input resistance of speaker 1.2 kW R8//Input resistance of sounder 150 W
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Semiconductor
MSM7586-01/03
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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